A CMOS imager circuit includes a focal plane array of pixel cells, each one of the cells including a photosensor, for example, a photogate, photoconductor or a photodiode overlying a substrate for accumulating photo-generated charge in the underlying portion of the substrate. Each pixel cell has a charge storage region, formed on or in the substrate, which is connected to the gate of an output transistor that is part of a readout circuit. The charge storage region may be constructed as a floating diffusion region. In some imager circuits, each pixel may include at least one electronic device such as a transistor for transferring charge from the photosensor to the storage region and one device, also typically a transistor, for resetting the storage region to a predetermined charge level prior to charge transference.
In a CMOS imager, the active elements of a pixel cell perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) resetting the storage region to a known state before the transfer of charge to it; (4) transfer of charge to the storage region accompanied by charge amplification; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge. Photo charge may be amplified when it moves from the initial charge accumulation region to the storage region. The charge at the storage region is typically converted to a pixel output voltage by a source follower output transistor.
CMOS imagers of the type discussed above are generally known as discussed, for example, in U.S. Pat. No. 6,140,630, U.S. Pat. No. 6,376,868, U.S. Pat. No. 6,310,366, U.S. Pat. No. 6,326,652, U.S. Pat. No. 6,204,524 and U.S. Pat. No. 6,333,205, assigned to Micron Technology, Inc., which are hereby incorporated by reference in their entirety.
A typical four transistor (4T) CMOS imager pixel 10 is shown in FIG. 1. The pixel 10 includes a photosensor 12 (e.g., photodiode, photogate, etc.), transfer transistor 14, floating diffusion region FD, reset transistor 16, source follower transistor 18 and row select transistor 20. The photosensor 12 is connected to the floating diffusion region FD by the transfer transistor 14 when the transfer transistor 14 is activated by a transfer gate control signal TX.
The reset transistor 16 is connected between the floating diffusion region FD and an array pixel supply voltage Vaa_pix. A reset control signal RST is used to activate the reset transistor 16, which resets the floating diffusion region FD to the array pixel supply voltage Vaa_pix level as is known in the art.
The source follower transistor 18 has its gate connected to the floating diffusion region FD and is connected between the array pixel supply voltage Vaa_pix and the row select transistor 20. The source follower transistor 18 converts the charge stored at the floating diffusion region FD into an electrical output voltage signal Vout. The row select transistor 20 is controllable by a row select signal SEL for selectively connecting the source follower transistor 18 and its output voltage signal Vout to a column line 22 of a pixel array.
FIG. 2 illustrates a typical imaging device 50 comprising a pixel array 56 containing multiple pixels 10 organized into a plurality of rows and columns. The device 50 also contains a row decoder 52, row driver 54, row operations and ADC (analog-to-digital converter) controller 58, a plurality of analog-to-digital converters 601, 602, . . . , 60n (collectively analog-to-digital converters 60), a static random access memory (SRAM)/read controller 66, a plurality of sample and hold (S/H) and amplifier circuits 721, 722, . . . , 72n (collectively S/H circuits 72), two memory banks 62, 64, sense amplifier circuitry 68 and a column decoder 70.
The S/H circuits 72 are connected to the column lines 22 of the array 56. The analog-to-digital converters 60 are connected to the S/H circuits 72 by what is commonly known as a column-parallel architecture. That is, in the illustrated imaging device 50, each column or column line 22 of the array 56 is connected to a respective analog-to-digital converter 60, which operate in parallel to convert analog signals from the array 56 (via the S/H circuitry 72) to digital signals.
The imaging device 50 is operated by the row operations and ADC controller 58, which controls the row driver 54 and the analog-to-digital converters 60. The row operations and ADC controller 58 also issues a sample control signal SAMPLE to the first memory bank 62, which is illustratively an SRAM device. The second controller, i.e., the SRAM/read controller 66 also controls the operation of the imaging device 50 by controlling the second memory bank 64, also an SRAM device (via a shift control signal SHIFT), and the column decoder 70.
In operation, row lines are selectively activated by the row driver 54 in response to the row decoder 52. The S/H circuits 72 input a pixel reset signal Vrst and a pixel image signal Vsig for selected pixels. A differential signal (Vrst-Vsig) is produced, by a differential amplifier within the S/H circuits 72, for each pixel and is digitized by the analog-to-digital converters 60. The digitizing of the data from each column is performed in parallel. The digitized signals are stored in the first memory bank 62 (when the sample control signal SAMPLE is issued) and subsequently shifted into the second memory bank 64 (when the sample control signal SAMPLE is issued). The sense amplifier circuitry 68 senses the stored digital data from the second memory bank 64 and outputs the digital information so that it may be processed by e.g., an image processor (not shown).
As described above, the analog-to-digital converters 60 of the illustrated imaging device 50 are connected in accordance with a column-parallel architecture. Some imaging devices, by contrast, have analog-to-digital converters connected using a serial architecture, whereby one analog-to-digital converter is used to convert the analog imager signals from all columns. The conversions are performed one column at a time in a serial manner.
The column-parallel architecture has several advantages over the serial architecture. Most notably, the column-parallel architecture consumes less power than the serial architecture while also offering comparable or lower (i.e., better) noise performance. This can be seen from the following comparisons.
Presume that the imaging device has an array comprising NH×NV pixels and operates at FR frames/s (i.e., it has a Frame time Tframe=1/FR). In the following equations, unless otherwise indicated, the subscript “S” is used for variables associated with the serial architecture and the subscript “CP” is used for variables associated with the column-parallel architecture. For simplicity purposes, the power consumption of a serial analog-to-digital converter is expressed as:PS=VAA·IAA—S,  (1)where VAA is a supply voltage and IAA is an average current flowing from VAA. The conversion rate can then be approximated as follows:
                                          f            CONV_S                    =                                                                      N                  H                                ·                                  N                  V                                                            T                frame                                      ⁢                                                  [            Hz            ]                          ,                            (        2        )            where, Tframe is the frame time.
The power consumption and conversion rate of a column-parallel analog-to-digital converter can be respectively expressed as:
                                          P            CP                    =                                    N              H                        ·                          V              AA                        ·                          I              AA_CP                                      ,        and                            (        3        )                                          f          CONV_CP                =                              1                          1              ⁢                                                          ⁢              H                                =                                                                      N                  V                                                  T                  frame                                            ⁢                                                          [              Hz              ]                        .                                              (        4        )            
From equations (2) and (4), the ratio of the required frequency bandwidth can be expressed as:
                                          Δ            ⁢                                                  ⁢                          f              CP                                            Δ            ⁢                                                  ⁢                          f              S                                      =                              1                          N              H                                .                                    (        5        )            
Assuming that an identical analog-to-digital converter is used for the column-parallel architecture, a power consumption ratio is derived as follows. The bandwidth of an analog circuit in the ADC is given by
                                          Δ            ⁢                                                  ⁢            f                    ∝                                    g              m                        C                          ,                            (        6        )            where gm is the “effective” transconductance of an amplifier and C is its “effective” load capacitance. Since the transconductance gm of a MOS transistor is proportional to √{square root over (IAA)}, i.e., gm, ∝√{square root over (IAA)}, the power consumption ratio may be represented by:
                                          P            CP                                P            S                          =                                                            N                H                            ·                              I                AA_CP                                                    I              AA_S                                =                                    N              H                        ·                                                            (                                                            g                      m_CP                                                              g                      m_S                                                        )                                2                            .                                                          (        7        )            
Plugging in equations (5) and (6) above, equation (7) can be represented as:
                                                        P              CP                                      P              S                                ⁢                                    N              H                        ·                                          (                                                      C                    CP                                                        C                    S                                                  )                            2                        ·                                          (                                                      Δ                    ⁢                                                                                  ⁢                                          f                      CP                                                                            Δ                    ⁢                                                                                  ⁢                                          f                      S                                                                      )                            2                                      =                              1                          N              H                                ·                                                    (                                                      C                    CP                                                        C                    S                                                  )                            2                        .                                              (        8        )            Thus, the power consumption in the column-parallel architecture becomes smaller than that of the serial architecture.
Amplifier thermal noise namp is proportional to Δf/gm as shown by the following equation:
                              n          amp          2                ∝                                            Δ              ⁢                                                          ⁢              f                                      g              m                                .                                    (        9        )            If the frequency bandwidth Δf is given by equation (6), then equation (9) becomes:
                              n          amp          2                ∝                              1            C                    .                                    (        10        )            
The kTC noise associated with a sample-and-hold operation has the same relationship as that shown by equation (10). Thus, the temporal noise in the column-parallel architecture is expected to be the same as the noise in the serial architecture, if the capacitance value is the same in both architectures. Although it is likely that CCP<CS, noise tends to mix in the serial approach since the distance between the column circuits and a serial ADC is much longer in the serial architecture.
Thus, the column-parallel architecture provides a low power, low noise digital-output CMOS imaging device (as compared to the serial architecture).
As can be seen from FIG. 2, in the conventional column-parallel analog-to-digital architecture, one analog-to-digital converter 60 is devoted/connected to one column of the pixel array 56. Sometimes, the analog-to-digital converters 60 are devoted/connected to more than one column of the pixel array 56. Although the column-parallel architecture offers operational benefits over the serial architecture, it does have some shortcomings. For example, the layout of an analog-to-digital converter with respect to column pitch, or a few times the column pitch, of the imaging device becomes increasingly difficult to implement as pixel sizes shrink to less than 3 μm. Although the column-parallel architecture may be used in these devices, the architecture requires a long and narrow layout for each analog-to-digital converter; this will use an extremely large area, which is expensive and undesirable.
Another potential shortcoming concerns the conversion speed of the conventional single slope (SS) analog-to-digital converter. That is, the conversion speed of the single slope analog-to-digital converter is not fast enough to for image sensors with high pixel count (e.g., greater than 2M pixels), analog-to-digital conversion resolution (e.g., greater than 12 bits) and/or video frame rate (e.g., greater than 60 frames per second (fps)).
As indicated earlier, it is possible to connect more than one column to an analog-to-digital converter in the column-parallel architecture. In situations where the column-parallel architecture is configured such that multiple columns share a successive approximation (SA) analog-to-digital converter or a single slope analog-to-digital converter, the analog-to-digital conversion is done in a somewhat sequential manner, as shown in FIG. 3. FIG. 3 illustrates the situation where four columns share the same analog-to-digital converter. During a first time interval 80, e.g., the horizontal blanking period (H-BL) of the imaging device 50, pixel outputs from the four columns of the row being read out ROW_i are sampled into the appropriate column S/H circuitry 72. Then, in the next time interval 82, e.g., the horizontal scanning period (H-SCAN) of the device 50, the analog-to-digital conversion of the ROW_i signals takes place, while the digital data generated in a previous row ROW_i−1 is read out.
FIG. 3 illustrates the situation where four columns of ROW_i are respectively converted during the ADC_0, ADC_1, ADC_2 and ADC_3 conversion periods. As shown in FIG. 3, the conversions ADC_0, ADC_1, ADC_2, ADC_3 are done sequentially. In a third time period 84, four columns from the next row ROW_i+1 are read out. The signals from ROW_i+1 are converted while the converted signals from ROW_i are output during the fourth illustrated time period 86. Thus, even though a column-parallel architecture is used, many of the conversions are still performed in a serial manner, which is undesirable.
Thus, the shortcomings of the current column-parallel analog-to-digital converter architecture makes is difficult to achieve a digital-output image sensor with small pixel size (e.g., less than 3 μm), high pixel count (e.g., greater than 2M-pixels), high ADC resolution (e.g., greater than 12 bits) and high video frame rate (e.g., greater than 60 fps). Accordingly, there is a need and desire for an analog-to-digital converter architecture that is suitable for use with an imaging device, such as a CMOS imaging device, having small pixel size (e.g., less than 3 μm), high pixel count (e.g., greater than 2M-pixels), high ADC resolution (e.g., greater than 12 bits) and high video frame rate (e.g., greater than 60 fps).